We investigate how to make faster hash maps, trees, linked lists and vector of pointers by changing their data layout.
All posts in Low Level Performance
Performance Through Memory Layout
In this post we investigate how we can improve the performance of our memory-intensive codes through changing the memory layout of our performance-critical data structures.
Measuring Memory Subsystem Performance
In this post we introduce a few most common tools used for memory subsystem performance debugging.
Hiding Memory Latency With In-Order CPU Cores OR How Compilers Optimize Your Code
We investigate techniques for hiding memory latency on in-order CPU cores. The same techniques that the compilers employ.
Software Performance and Class Layout
We investigate the secret connection between class layout and software performance. And of course, how to make your software faster.
Decreasing the Number of Memory Accesses: The Compiler’s Secret Life 2/2
We investigate memory loads and stores that the compiler inserts for us without our knowledge: “the compiler’s secret life”. We show that these loads and stores, although necessary for the compiler are not necessary for the correct functioning of our program. And finally, we explain how you can improve the performance of your program by removing them.
Decreasing the Number of Memory Accesses 1/2
In this post, we are investigating a few common ways to decrease the number of memory accesses in your program.
Frugal Programming: Saving Memory Subsystem Bandwidth
We investigate techniques of frugal programming: how to program so you don’t waste the limited memory resources in your computer system.
For Software Performance, the Way Data is Accessed Matters!
In our experiments with the memory access pattern, we have seen that good data locality is a key to good software performance. Accessing memory sequentially and splitting the data set into small-sized pieces which are processed individually improves data locality and software speed. In this post, we will present a few techniques to improve the…
When an instruction depends on the previous instruction depends on the previous instructions… : long instruction dependency chains and performance
This post has a second part, the same problem is solved differently. Read more. In this post we investigate long dependency chains: when an instruction depends on the previous instruction depends on the previous instruction… We want to see how long dependency chains lower CPU performance, and we want to measure the effect of interleaving…