In this post we talk about memory mechanism that increase memory accesses latency and we explore the techniques to avoid them in latency-sensitive systems.
All posts tagged tlb cache
Speeding Up Translation of Virtual To Physical Memory Addresses: TLB and Huge Pages
In this post we explore how to speed up our memory intensive programs by decreasing the number of TLB cache misses
Measuring Memory Subsystem Performance
In this post we introduce a few most common tools used for memory subsystem performance debugging.
The memory subsystem from the viewpoint of software: how memory subsystem affects software performance 2/3
We continue the investigation from the previous post, trying to measure how the memory subsystem affects software performance. We write small programs (kernels) to quantify the effects of cache line, memory latency, TLB cache, cache conflicts, vectorization and branch prediction.
Memory consumption, dataset size and performance: how does it all relate?
We investigate how memory consumption, dataset size and software performance correlate…